Published on Jun 05, 2023
The proliferation of wireless products over past few years has been rapidly increasing. New wireless standards such as GPRS and HSCSD have brought new challenges to wireless transceiver design. One pivotal component of transceiver is frequency synthesizer.
Two major requirements in mobile applications are efficient utilization of frequency spectrum by narrowing the channel spacing and fast switching for high data rates. This can be achieved by using fractional- N PLL architecture. They are capable of synthesizing frequencies at channel spacings less than reference frequency. This will increase the reference frequency and also reduces the PLL's lock time.
Fractional N PLL has the disadvantage that it generates high tones at multiple of channel spacing. Using digital sigma delta modulation techniques. we can randomize the frequency division ratio so that quantization noise of the divider can be transferred to high frequencies thereby eliminatory the spurs. The advantages of this conventional PLL modulator is that they offer small frequency resolution, wider tuning bandwidth and fast switching speed. But they have insufficient bandwidth for current wireless standards such as GSM.
So that they cannot be used as a closed loop modulator for digital enhanced codeless (DECT) standard. they efficiently filter out quantization noise and reference feed through for sufficiently small loop bandwidth.
